Job Summary

You build the software infrastructure that makes novel hardware actually usable, and you help shape what that hardware looks like in the first place. At Opticore, you will work alongside our Computer Architect to co-design the ISA and execution model, then own the compiler stack that targets it: from high-level ML model representations down to efficient execution on our photonic computing platform. This is a senior, software-focused role, but you will be in the room for hardware decisions from day one. Your job is to make sure the architecture is one a compiler can actually exploit, and then prove it by building that compiler.

Key Responsibilities

• •Partner with the System Architect to co-define the ISA, execution model, and hardware-software interface, ensuring architectural decisions are compiler-friendly from the start
• •Design and implement the compiler stack for Opticore's photonic platform: IR design, lowering passes, code generation, and runtime interfaces
• •Map LLM and AI inference workloads to photonic execution: tiling, scheduling, memory layout, and operator fusion
• •Build performance analysis and profiling infrastructure to identify bottlenecks and guide optimization
• •Maintain close, ongoing collaboration with the hardware team, translating hardware constraints into compiler representations and feeding compiler observations back into hardware design
• •Contribute to the runtime layer: memory management, execution scheduling, and host-device communication

Minimum Requirements

• •7+ years of hands-on compiler engineering experience (MLIR, LLVM, TVM, XLA, or equivalent)
• •Experience lowering ML workloads onto custom or non-standard hardware targets
• •Ability to read and reason about hardware architecture (memory hierarchies, dataflow models, execution pipelines) and participate meaningfully in ISA and execution model design
• •Track record of working directly with hardware teams to jointly define and refine the hardware-software interface
• •Seniority to drive technical decisions independently and influence architecture choices upstream
• •Comfort building from scratch in an environment where the target architecture is co-evolving with the software

Even Better If You Have

• •Experience targeting novel or non-von-Neumann accelerators (photonic, analog, neuromorphic, custom ASIC)
• •Background in quantization, sparsity, or other model-level optimizations with hardware implications
• •Familiarity with kernel-level optimization (e.g., Triton, CUDA, or custom kernel authoring for accelerators)
• •Prior experience contributing to an ML framework backend (PyTorch, JAX, etc.)

We're reviewing applications on a rolling basis and will reach out to shortlisted candidates.